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900 MHz Dual Pin Electronics Driver, Window Comparator, and Load
TEST AND MEASUREMENT PRODUCTS Description
The EDGE7725 dual channel, monolithic ATE pin electronics solution is manufactured in a high-performance complementary bipolar process. The EDGE7725 operates greater than 900 MHz/1.8 Gbps. The power supplies to the EDGE7725 are specified over a wide range to accommodate between -2V, +7V and -0.5V, +4.2V input, output voltages. The three-statable EDGE7725 tri-level driver is capable of generating 8V swings over a -2 to +7V range, with a minimum swing of 100 mV. The driver's third level is used when the driver acts as a switched termination, and the load is not being used. The differential driver mode permits the inverse of DHI driving of Channel 0 to be output on Channel 1, creating differential outputs having a minimum of skew. An input power down mode lowers the DOUT leakage current. The EDGE7725 window comparator can span a 9V common mode range. Programmable voltage clamps at the input to the comparator provide a means to clamp voltage overshoots and excessive ringing for unterminated comparator input signals. An input power down mode lowers the VINP input leakage currents. The EDGE7725 differential comparator can compare input differences of up to 800mV to input levels which are separate from those of the window comparators. The EDGE7725 load supports programmable source and sink currents of 32 mA over a -2V to +7V range, or it can be completely disabled. The load may be configured as a "split load" whereby the load can act as a voltage clamp as an alternate to the comparator's clamp. For operating modes requiring no load, the EDGE7725's load may be depowered to conserve power.
EDGE7725
Features
* Fully Integrated Three-Statable, Tri-Level Driver, Window Comparator, and Dynamic Active Load * Wide Choice of Range, Performance vs. Power * Differential Driver and Comparator Modes * Programmable Driver Rise, Fall Times * Programmable Voltage Clamps on Comparator Input * -2V, +7V Driver, Compare, Load Range * 32 mA Programmable Load * Comparator Input Tracking to >3V/ns * Small, 128-Pin MQFP Package
Applications
* * * * * Logic Testers Mixed-Signal Test Equipment Memory Testers Flash Memory Testers ASIC Verifiers
Functional Block Diagram
Channel 0
VCM_IN VCM_OUT SNK VEE RADJ DOUT FADJ QA SEL QB DHI CVC[0] SEL_DHI SEL CVC[1] DHI QB SEL QA DH DEN LEN SEL DT LE VEE LOUT VCC CATHODE CVB VCL VINP VCH CVA RADJ DOUT FADJ CVA VCH VINP VCL CVB LOUT VCC
LE LEN DEN SEL DT DH
SNK VCM_OUT VCM_IN
Channel 1
ANODE
Revision 9 / August 22, 2006
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EDGE7725
TEST AND MEASUREMENT PRODUCTS PIN Description
[0:1] Refers to Channels 0 or 1
Pin # Control 17, 22 16, 23 21 18 Driver 105, 106; 61, 62 89, 78 90, 77 91, 76 92, 75 98, 69 96, 71 94, 73 103, 64 102, 65 86, 81 Comparator 128, 39 3, 36 2, 37 1, 38 10, 29 11, 28 122, 45 121, 46 123, 44 124, 43 7, 32 VINP[0:1] CVA[0:1] CVB[0:1] CVC[0:1] VCH[0:1] VCL[0:1] QA[0:1] QA*[0:1] QB[0:1] QB*[0:1] CBIAS[0:1] Analog voltage input to the positive input of the A and B comparators. Analog inputs which set the A, B, and C comparator thresholds. DOUT[0:1] DHI[0:1] DHI*[0:1] DEN[0:1] DEN*[0:1] DVH[0:1] DVL[0:1] DVT[0:1] RADJ[0:1] FADJ[0:1] DBIAS[0:1] Driver output. Flex differential input digital pins which select the driver high or low CONFA[0:1] CONFB[0:1] SEL_DHI SEL_CMP TTL inputs to configure the mode of the channel. TTL inputs to configure the mode of the channel. TTL input that selects the Differential Drive Mode when a logical high. TTL input that selects window comparators or differential comparator. Differential comparator is selected when SEL CMP is a logical high. Pin Name Description
Flex differential input pins which control the driver being active or in a high impedance state. High impedance analog voltage inputs which determine the driver high, low, and termination levels. Input currents which determine the driver transition, rise and fall times. Analog current input that sets an internal bias current for the driver.
Voltage clamp high and low inputs. Differential digital outputs of comparators A and B.
Analog current input that sets an internal bias current for the comparator. Ground sense line for the differential comparator circuit. Connect to ground reference for the CVC[0:1] voltage level generating circuit.
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120, 47
CVC_GND[0:1]
(c)2006 Semtech Corp. , Rev. 9, 8/22/06
EDGE7725
TEST AND MEASUREMENT PRODUCTS PIN Description (continued)
[0:1] Refers to Channels 0 or 1
Pin # Load 114, 53 85, 82 84, 83 118, 49 117, 50 108, 59 112, 55 113, 54 111, 56 Power Supplies 12, 13, 14, 15, 101, 107, 115, 116, 24, 25, 26, 27, 51, 52, 66, 60 4, 5, 6, 33, 34, 35, 40, 57, 58, 63, 70, 72, 79, 80, 87, 88, 95, 97, 104, 109, 110, 127 126, 125, 42, 41 8, 9, 93, 99, 100; 119, 74, 30, 31, 48, 67, 68 Miscellaneous 19, 20 ANODE, CATHODE Terminals of the on-chip thermal diode string. VCC[0:1] Positive power supply. See pin diagram for notations of which pins supply power for which circuit functions. LOUT[0:1] LEN[0:1] LEN*[0:1] ISC_IN[0:1] ISK_IN[0:1] VCM_IN[0:1] VCM_OUT[0:1} VCM_CAP[0:1] SNK[0:1] Load Output Flex differential inputs which activate and disable the load or driver trilevel. Analog current inputs which program the load source and sink currents. Should be connected to external voltage or current source through minimum 500 (min.) series resistors. High impedance analog voltage inputs that program the commutating voltage. Commutating voltage buffer output. Commutating buffer op amp compensation pins (10 nanofarad, high frequency). Sink input current to load. Pin Name Description
VEE
Negative power supply. Common for all circuit functions. Internally connected together. NOTE: Exposed heat slug is connected to VEE.
PECL[0:1] GND[0:1]
Positive power supply to the comparators. Device ground. See pin diagram for notations of which pins supply ground for which circuit functions.
Note 1:
All VEEs must be connected, externally, to the same supply. All VCCs must be connected, externally, to the same supply. All PECLs must be connected, externally, to the same supply. All GNDs must be connected, externally.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS PIN Description (continued)
Pack ackage 128 Lead MQFP Package (Top) with Exposed Heat Slug (Top)
LOAD[0] DRIVER[0]
CVC[0] CVB[0] CVA[0] VEE VEE VEE CBIAS[0] COMPARATOR[0] GND[0] GND[0] VCH[0] VCL[0] VCC[0] COMPARATOR[0] VCC[0] VCC[0] VCC[0] CONFB[0] CONFA[0] SEL_CMP ANODE CATHODE SEL_DHI CONFA[1] CONFB[1] VCC[1] COMPARATOR[1] VCC[1] VCC[1] VCC[1] VCL[1] VCH[1] COMPARATOR[1] GND[1] GND[1] CBIAS[1] VEE VEE VEE CVA[1] CVB[1] CVC[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
FADJ[0] VCC[0] GND[0] GND[0] DVH[0] VEE[0] DVL[0] VEE[0] DVT[0] GND[0] DEN*[0] DEN[0] DHI*[0] DHI[0] VEE VEE DBIAS[0] LEN[0] LEN*[0] LEN*[1] LEN[1] DBIAS[1] VEE VEE DHI[1] DHI*[1] DEN[1] DEN*[1] GND[1] DVT[1] VEE[1] DVL[1] VEE[1] DVH[1] GND[1] GND[1] VCC[1] FADJ[1] DRIVER[1] DRIVER[1] DRIVER[0] DRIVER[0]
128 Lead 14 x 20 x 2.0 mm Footprint 23.2 x 17.2 mm Top View
LOAD[1]
DRIVER[1]
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Circuit Description
Introduction Figure 1 shows a detailed block diagram of the EDGE7725. Table 1 shows the modes of the EDGE7725 as configured by the TTL inputs, CONFA and CONFB. These "configuration" inputs will put the channel's driver, comparator, and load circuits into specific operating modes and power down states. The configuration inputs are asynchronous and, therefore, when they are switching from one state to another, there could be decoding glitches. The user should be aware of this and keep the skew among the three inputs to a minimum to minimize any unwanted conditions at the driver and load outputs. It is also recommended that the driver and load outputs be disabled when changing modes. NOTE: Do not leave the CONF inputs floating. They should be forced to valid high or low logic levels at all times.
Mode
Conf Mode Inputs B A
Internally Pow ered Dow n DHI
Driver, Load Control D EN LE N DOUT
Function States LOAD COMP CLAMPS Comments
All Off
0
0
0
Driver, Load, Comp, Clamp
X 0 1
X 1 1 0 1 1 0 1 1 1 0 1 1 0
X 0 0 0 1 1 1 0 0 1 X X X X
Off D VL D VH HiZ D VL D VH HiZ D VL D VH D VT HiZ D VL DVH HiZ
Off
Off
Off
Powered Down, Low Leakage Mode
Off On On On Driver, Comparator, and Load Enabled (no Driver Tri-Level) (Clamps On)
Drive/ Receive Pin
1
0
1
None
X 0 1 X 0
Drive/ Receive Pin w ith D VT
2
1
0
Load
1 X X 0
Off
On
Off
Driver, Comparator Enabled. Driver Tri-Level Clamps Off (No Load) Driver Enabled, (No Load, Comparator, or Driver Tri-Level). (Clamps Off)
Drive Pin
3
1
1
Load, Comp, Clamp
1 X
Off
Off
Off
KEY: - X (Don't Care) - DVH (Drive High) - DVL (Drive Low) - DVT (Drive third, termination level) - HiZ (High Impedance)
NOTE: The entire table above is valid for SEL_CMP and SEL_DHI in any high or low state.
Table 1: EDGE7725 Modes of Operation (c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
CONFA[0] CONFB[0] LEN[0] LEN*[0] VCM_CAP[0] VCM_IN[0] VCM_OUT[0] SNK[0] SEL DT
Channel 0 VC_OFF PD_C,D,L
LE VCC[0] ISC_IN[0] LOUT[0] ISK_IN[0] VEE
PD_L
DBIAS[0] DVH[0] DT DEN[0] DEN*[0] DE DH DVL[0] DVT[0] PD_C PD_D SEL_CMP VCC VC_OFF RADJ[0] DOUT[0] FADJ[0]
QA*[0] QA[0] CBIAS[0], PECL[0] QB[0] QB*[0] DHI[0] DHI*[0]
CVA[0] VCH[0] VINP[0] VCL[0] CVB[0]
VEE
CVC[0] SEL_DHI SEL SEL CVC_GND[0:1] CVC[1] VEE
DHI*[1] DHI[1] QB*[1] QB[1] CBIAS[1], PECL[1] QA[1] QA*[1]
CVB[1] VCL[1] VINP[1] VCH[1] CVA[1]
PD_C DVT[1] DVL[1]
VCC
VC_OFF
PD_D
DH
DEN*[1] DEN[1]
FADJ[1] DOUT[1] RADJ[1]
DE DT
DVH[1] DBIAS[1] VEE ISK_IN[1] SNK[1] VCM_OUT[1] ISC_IN[1] VCM_IN[1] VCM_CAP[1] LEN*[1] LEN[1] CONFA[1] CONFB[1] VCC[1] DT SEL LE PD_L LOUT[1]
VC_OFF PD_C,D,L Channel 1
ANODE
CATHODE
Figure 1. EDGE7725 Detailed Block Diagram (c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Driver Both driver digital control inputs (DHI/DHI*, DEN/DEN*) are "Flex Inputs" - wide voltage differential inputs capable of receiving ECL, TTL, CMOS, or custom level signals. Singleended operation is supported by connecting the inverting input to the appropriate DC threshold level. Differential input drive is recommended for highest performance. Drive Enable In the driver enabled mode (Table 1), the drive enable inputs (DEN / DEN*) control whether the driver is forcing a voltage, or is placed in a high-impedance state. If DEN is more positive than DEN*, the output will force either DVH, DVL, or DVT. If DEN is more negative than DEN*, the output goes into a high impedance state. NOT leav Do NOT leave DEN / DEN* floating. Driver Data When the driver is enabled (Table 1) the drive data inputs (DHI / DHI*) determine whether the driver output is forcing a high or a low. If DHI is more positive than DHI*, the driver will force DVH when the driver is active. If DHI is more negative than DHI*, the driver will force DVL when active. NOT leav Do NOT leave DHI / DHI* floating. Driver Differential Mode Selection The TTL input SEL_DHI selects the channel from which the DHI/DHI* signal is applied to each driver.
Rext
Driver Tri-Level When the load is not being used (Table 1) and the driver is enabled, then (LEN/LEN*) will switch the driver to its third level, DVT, independent of DHI, whereupon the driver can act as a termination inclusive of an external series resistor (e.g. driver can act as a switched 50 termination). NOT leav Do NOT leave LEN / LEN* floating. Driver Levels DVH, DVL, and DVT are high input impedance voltage inputs which establish the driver's high, low, and third (termination) levels. Bias Inputs The DBIAS, CBIAS, RADJ and FADJ input pins are analog current inputs which establish on-chip bias currents. These currents, to some degree, also establish the overall power consumption and performance of the circuits. Ideally, an adjustable external current source would be used to finetune and minimize any part-to-part performance variation within a test system. However, a precision external resistor tied to a large positive voltage is typically acceptable. (See figure below.) The optimal settings are dependent on required system performance and power requirements. The established bias currents have the typical circuit below and follow the equation: BIAS = (VCC - 0.7) / (Rext + 462).
S E L _D H I 0 1
DH[0] from: DHI/DHI*[0] DHI/DHI*[0]
DH[1] from: DHI/DHI*[1] DHI*/DHI[0]
BIAS 462
VCC
SEL_DHI = 1 is used for outputting a differential signal where DOUT[1] is the inverse of DOUT[0] with the minimum of skew, and both drivers respond to the DHI/DHI*[0] signal. The DEN/DEN* signals are still valid when the drivers are in the differential mode.
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(c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Driver Power Down Modes Referring to Table 1, Mode 0, "ALL_OFF" is a configuration in which the driver can be put into a power down mode (reducing power supply currents, power dissipation and output leakage currents), and others in which the driver is powered and ready for operation. Driver Slew Rate Adjustment The driver rising and falling transition times are independently adjustable. The RADJ and FADJ pins are analog current inputs which establish the driver rise and fall times. Ideally, an adjustable external current source would be used for RADJ and FADJ. However, for applications where the rise and fall times are fixed, precision external resistors to a positive voltage can be used. The currents into RADJ and FADJ follow the equation: RADJ, FADJ = (VCC - 0.7) / (Rext + 550).
Rext RADJ, FADJ 550 VCC
Rise/Fall Adjust Current VEE
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Window Comparator Two comparators are connected on-chip to form a window comparator to determine whether the DUT is high, low, or in an intermediate state. VINP is tied to the positive inputs of both comparators. The selection of either comparator A or B for the DUT high or the DUT low comparison is arbitrary. The figure below shows the correct polarity for the comparator connections.
VCC Clamp Enable (Internal Signal)
The QA, QA*, QB, QB* output voltages are relative to the PECL supply voltage input. The DC Specifications section will specify the differential output voltage swings and common mode voltages to expect. Differential Amplifier and Comparator VINP[0], VINP[1] are also input to a differential amplifier. The differential amplifier output (VINP[0] minus VINP[1]) is then compared against CVC[0] and CVC[1] inputs over a 800mV range, where 0.1V < |VINP[0] - VINP[1]| < 0.8V
QA* QA CBIAS QB QB*
CVA VCH VINP VCL CVB
The figure below is a functional diagram of the window and differential comparators.
SEL_CMP CVA[0] VINP[0] CVC[0] CVC_GND[0]
A
QA[0] QA*[0]
D0
VEE
CH[0] Window Comparator B
Comparator truth table, where CVA > CVB:
QA V INP > C VA C V B < V INP < C VA V INP < C V B H L L QB H H L
CVB[0]
QB[0] QB*[0]
CVA[1]
A
QA[1] QA*[1]
VINP[1] CVC[1] CVC_GND[1]
D1
CH[1] Window Comparator B QB[1] QB*[1]
CVB[1]
Thresholds CVA and CVB are the window comparator's two threshold levels. These inputs are high impedance voltage controlled inputs that determine at which VINP voltage the comparators will change output states. CVC[0], CVC[1] are the two differential comparator's threshold levels. The window and differential comparators cannot be used at the same time because they share output pins QA, QA*, QB, QB*. Since they are not used at the same time, the compare voltages can be shared between the window and differential comparators to save in reference level DACs and power. CVC[0] may be connected to CVA[0] or CVB[0], and the same is true for CVC[1], CVA[1] and CVB[1].
(c)2006 Semtech Corp. , Rev. 9, 8/22/06
The difference amplifiers will subtract the voltage at VINP[1] from VINP[0] and the result is presented to a comparator that compares this result against an input voltage CVC[0] or CVC[1]. These input voltages may well be referenced to a different ground than analog ground at the E7725. They more than likely will be referenced to a buffered version of the DUT ground. In order for the difference amplifiers to operate correctly each of the them has a ground reference input, CVC_GND[0:1]. This high impedance input should be connected to the ground reference point of the level DAC that is generating the CVC[0] and the CVC[1] voltages respectively. The voltages at CVC_GND[0:1] can be +/-0.25V from analog ground at the E7725.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Differential Comparison Example
VINP[0] 800 mV VINP[1] VINP[0] - VINP[1] CVC[0] CVC[1] Inputs into Differential Buffer
+800 mV +700 mV -600 mV -800 mV
Inputs into Differential Comparator
line between the device and the E7725 is not terminated. This signal can then be reflected back to the test device, potentially stressing or damaging the device. Subsequent reflections can also cause false triggers in the timing circuitry that receive the comparator outputs. So, the clamps limit the minimum and maximum amplitude of the signal when it reaches the comparator input. Under transient conditions, these clamps will source or sink relatively large amounts of current as needed to limit the voltage. Under DC conditions (after ~100 ns), however, the maximum current is limited to a lower current. This is done to limit the amount of power dissipation under fault conditions. For instance, if the VCH voltage is set to 3V when the part being tested puts out 5V. See the figure below for clamp current vs. input voltage curves. The "clamps off" mode (Table 1) causes the internal clamp levels to be set outside the operating range, independent of VCH or VCL inputs. Clamp characteristic:
Current AC Clamp Current VCL VCH DC Clamp Current 0.35V 2V 0.6V < +100A >20mA >1mA <-1mA <-20mA 0.6V 0.35V 2V
QA
DUT High
QB
DUT Low
Comparator Outputs (SEL_CMP = 1) (QA*, QB* are inverse of QA, QB)
Comparator Selection The TTL input SEL_CMP selects the comparators for output on QA, QB[0] and QA, QB[1]. SEL_CMP in a low state is the normal window comparator mode. The outputs of the window comparators A & B for each channel are output to their respective Q and Q* outputs. SEL_CMP in the high state enables the differential comparator mode. The outputs of the differential comparators are fed to the Q and Q* outputs for both channel 0 and 1. NOTE: Refer to the preceding functional diagram. The D0 and D1 differential comparators will output to QA[0] and QB[0], respectively, but they output to QB[1] and QA[1], respectively, also. Either pair of outputs may be used. The table below further clarifies this.
Comparator Output Mapping
SEL_CMP QA[0] QB[0] QA[1] QB[1]
Voltage
> -100A
0
CVA[0] Window Comparator CVC[0] Differential Comparator
CVB[0] Window Comparator CVC[1] Differential Comparator
CVA[1] Window Comparator CVC[1] Differential Comparator
CVB[1] Window Comparator CVC[0] Differential Comparator
1
Waveform Clamps VCH and VCL provide for programmable voltage clamps to the comparator input, VINP. These clamps are used when a device being tested is not designed to drive a 50 transmission line load. In such a case, the signal from the test device can be amplified to almost double the original voltage if the output impedance of the test device is very low, and the 50 transmission
Refering to Table 1, where the clamps are in the ON condition, it is still possible to turn the clamps off by setting the VCL voltage level above the VCH level. By reversing the operating polarity, the clamps will turn off. The VCH and VCL levels should still remain in their recommended operating ranges. Comparator Input Protection VINP is also connected to protection diodes to VCC and VEE as shown on the previous page. These diodes can handle up to 100 mA.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Comparator Power Down Modes Referring to Table 1, the comparators can be placed in a power down mode in certain configurations. Other configurations have the comparators powered and ready for operation. When the comparator sections are put into one of the power down modes, the QA, QA*, QB, QB* outputs are placed in a fixed differential logic state. The state could be a logic "0" or "1" depending upon internal levels at the time the circuit enters the power down mode. The outputs will not respond to changes at the VINP pins when in power down modes. Minimum leakage occurs when CVA, CVB > VINP. The load is capable of sourcing and sinking at least 32 mA dynamically, or being placed into a high impedance state. Load Enable LEN/LEN* are "Flex In" - wide voltage differential inputs capable of receiving ECL, TTL, CMOS, or custom levels. Single-ended operation is supported by connecting the inverting input to the appropriate DC threshold level. When the load is powered on (Table 1), the load enable differential inputs determine whether the load is active or in high impedance. If LEN is more positive than LEN*, the load is active and is capable of sourcing and sinking currents. If LEN is more negative than LEN*, the load is placed into a high impedance state (disabled). NOT leav Do NOT leave LEN / LEN* floating.
Load
The load is configurable as a split or non-split load:
VCM_CAP_A VCM_IN_A VCM_OUT_A External Buffer SNK (b)
A
LOUT (a)
Link (a): Non-Split Load Link (b): Split Load
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Load Commutating Voltage The load has one commutating voltage input, or two if used as a "split load". The following describes the "non-split" load operation. The "split load" operation is similar. VCM_IN is a high input impedance analog voltage input which sets the commutating voltage of the load. If DUT is more positive than VCM_IN, the bridge will sink current from the DUT into the load. If DUT is more negative than VCM_IN, the load will source current from the load into the DUT. Load Source and Sink Current Levels The amount of current that the diode bridge can source and sink is adjustable from 0 mA to 32 mA. The source and sink levels are separate and independent. ISC_IN and ISK_IN are current controlled inputs whose voltage level is held very close to ground (<100 mV variation) over the entire legal current input range. There is a nominal gain of 20 between the ISC_IN current and the bridge source current. ISOURCE = 20 * ISC_IN
VCM_IN DUT
There is a nominal gain of -20 between the ISK_IN current and the bridge sink current. ISINK = -20 * ISK_IN
VCM_IN Load Sinking Current: DUT > VCM_IN
To avoid instabilities in the circuit, care should be given to avoid capacitive coupling of the ISC_IN and ISK_IN inputs to the LOUT output.
VCM_IN
DUT
Sourcing VCM_IN Loading Sourcing Current: DUT < VCM_IN
VCM_CAP 10 nF VCM_IN
ISOURCE = (20) * ISC_IN
LOUT VCM_OUT SNK ISINK = (-20) * ISK_IN
0.1 F
Load Commutating Voltage (c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Load Commutating Voltage Compensation The VCM_CAP pin is an op amp compensation node that requires a fixed 10 nanofarad chip capacitor (with good high frequency characteristics) to ground. This capacitor is used to compensate an internal node on the on-chip buffer for the commutating voltage input. The VCM_OUT is the actual commutating voltage generated by the on-chip buffer. VCM_OUT is also connected to the diode bridge. A capacitor of 0.1 F to ground is also needed on the VCM_OUT pin for high speed switching of the load currents. Load Power Down Mode Referring to Table 1, the load circuit can be placed in the power down state in certain configurations which reduces overall power consumption. In other configurations, the load remains powered and ready for operation. Thermal Monitor An on-chip thermal diode string of five diodes in series exists (see figure below). This string allows accurate die temperature measurements. An external bias current of 100 A is injected through the string, and the measured voltage corresponds to a specific junction temperature with the following equation: Tj[C]={(ANODE - CATHODE) / 5 - 0.768} / (-0.00169).
ANODE
Power Supply Sequencing In order to avoid the possibility of latch-up, the following power-up requirements must be satisfied: 1. 2. 3. VEE < GND < VCC at all times VEE < Analog Inputs < VCC VEE < Digital Iputs < input max voltage or VCC, whichever is less
The following sequencing can be used as a guideline when powering up the EDGE7725: 1. 2. 3. 4. VEE VCC Digital Inputs Analog Inputs
The recommended power-down sequence is the reverse order of the power-up sequence.
Bias Current
Temperature Coefficient = -7.9 mV / C
CATHODE
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Application Information
Computing the Driver Output Voltage Range The output voltage range of the driver at the DOUT pin is defined by two fundamental calculations. First is the relationship to the power supply voltages at the device (VCC and VEE) and second to the range of programmability of the DVH, DVL and DVT input voltages. Remaining in the calculated output voltage range is required to maintain all the DC and AC accuracy specifications for the driver function. The DOUT range relative to the power supply voltages is straightforward and depicted in the following figure at the output of the driver. The required DOUT range must comply with the noted headrooms to the VCC and VEE power supplies. Headrooms larger than noted are also acceptable but must remain within the power supply recommended operating ranges.
VCC
inputs will have voltage offsets and gain error specifications. These specifications require that the DVH/L/T input programming range be greater than the required DOUT voltage range if the worst case offset and gain figures are used. The equation for the resulting minimum and maximum voltage at DOUT is; VDOUT(MIN/MAX) = VOFFSET(MIN/MAX)+[ VIN * GAIN(MIN) ] Solving for VIN; VIN = [ VDOUT(MIN/MAX) = VOFFSET(MIN/MAX) ] / GAIN(MIN) To solve for the range of VIN, first select the Vout ranges required. For example, if we choose -2.0V for the minimum end and +6.5V for the maximum end of VDOUT, and an offset min/max of -100mV/+100mV and a minimum gain of 0.975 the equations solve as; For -2.0V; VIN(-2V) = [ -2.0V - 100mV ] / 0.975 = -2.154V For +6.5V; VIN(+6.5V) = [ +6.5V + 100mV ] / 0.975 = +6.769V These resulting VIN values then need to meet the headroom requirements previously mentioned as well as the absolute (relative to ground) voltage limitations specified in the DC specifications data. Computing the Load Commutating Voltage Range The load circuit also has power supply headroom requirements similar to the driver circuit mentioned previously in order for the load circuit to maintain its DC accuracy specifications. The figure below shows the necessary headrooms for LOUT, VCM_IN and VCM_OUT. There is an additional voltage restriction between VCM_IN (and therefore VCM_OUT) and a voltage being impressed on LOUT. This maximum is 10.0V of either polarity.
3.5V
4.0V
3.8V
D V H
D V L
or
DVH
DOUT
D O U T
DVL
T
4.0V
3.5V
3.7V
VEE
The DOUT range is also dependant on the allowable programming voltages at the DVH, DVL and DVT inputs. Each of these inputs have similar requirements for power supply headrooms as DOUT does. These headrooms are also depicted in the above figure. Furthermore, the DVH/L/T
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
VCC
Refer to the DC specifications data to insure that the absolute (relative to ground) voltage restrictions are not violated.
3.8V
3.5V
3.8V MAX = +/-10v
VCC
V C M I N
V C M O U T
3.8V
ISC VCM_IN
3.65V
3.8V
VCM_OUT
L O U T
SNK
ISK
V C L
3.7V
V C H
C V A
or
VCH
CVA
A B
CVB
VINP
3.5V
3.7V
C V B
5.5V
V I N P
VCL
VEE
3.7V
3.6V
3.7V
The LOUT restriction of headroom to the power supplies is identical to the restriction placed on the VCM_OUT pin. Because there is a possible offset from VCM_IN to VCM_OUT the headroom restriction for the VCM_IN input is lower. This allows the VCM_IN pin to be adjusted higher to account for the worst case offset of the buffer amplifier. LOUT and VCM_IN inputs also have with them restrictions on absolute (relative to ground) voltage limitations. Refer to the DC specifications data for these values. Computing the Comparator and Clamp Input Voltage Ranges The window comparator and clamp circuitry are have headroom requirements also. The next figure depicts the requirements. Because the offsets and hysteresis of the comparators are so low (as compared to some driver and load offsets) there is no need to allow for special considerations in the restrictions. Once the user chooses the VINP operating range, the CVA, CVB, VCL and VCH operating areas will follow naturally with no special consideration for offsets needed.
VEE
Input Levels From Table 1, the load function is only operable when the driver tri-level is off (not used). Hence, input levels to these may be shared. For example, DVT may be connected to VCM-IN.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
Computing Maximum Power Consumption The diagram below shows the power consumption of the EDGE7725 as a function of power supply and performance bias settings.
Pow Dissipation er
Covers Complete Range of Supplies and Modes 11.0 10.0 9.0
adjustments available. Use the data and graphs in subsequent sections to determine a particular applications power dissipation. Another variable that needs to be determined is the maximum ambient air temperature that will be surrounding or blowing on the device and/or the heatsink system in the application (assuming an air cooled system). A heatsinking solution should be chosen to be at or below a certain thermal impedance known as R in units of C/Watt. The heatsinking system is a combination of factors including the actual heatsink chosen and the selection of the interface material between the EDGE7725 and the heatsink itself. This could be thermal grease or thermal epoxy, and they also have their own thermal impedances. The heatsinking solution will also depend on the volume of air passing over the heatsink and at what angle the air is impacting the heatsink. There are many options available in selecting a heatsinking system. The formula below shows how to calculate the required maximum thermal impedance for the entire heatsink system. Once this is known, the designer can evaluate the options that best fit the system design and meet the required R. R(heatsink_system) = (TJmax - Tambient- P * JC) / P where, R (heatsink_system) is the thermal resistance of the entire heatsink system TJmax is the maximum die temperature (100C) Tambient is the maximum ambient air temp expected at the heatsink (C) P is the maximum expected power dissipation of the EDGE7725 (Watts) JC is the thermal impedance of the EDGE7725 junction to case (0.53C/W) The following graph uses the power estimates from the previous graph and indicates the required maximum thermal impedances required for the heatsinking system using the above formula with Tambient at 35C.
Power (W)
8.0 7.0 6.0 5.0 4.0 3.0 2.0 Lowest Supplies Mode0 Lowest Supplies Mode1,2,3 (Max Loads) DUTIO-2/+7 Supplies Mode0 DUTIO-2/+7 Supplies Mode1,2,3 (Max Loads) Highest Supplies Mode0 Highest Supplies Mode1,2,3 (Max Loads)
The power consumption goes up as the power supplies are raised in voltage, modes are changed, and load circuits are programmed. Refer to the Specifications Section for choosing the power supply settings for a particular system voltage range. This section deals with how to heatsink the various power dissipation levels. Cooling Considerations Depending on the applied power supply levels and bias conditions the EDGE7725 will use, various methods of heatsinking will be required to keep the maximum die junction termperature within a safe range and below the specified maximum of 100C. The EDGE7725 package has an integral heat slug located at the top side of the package to efficiently conduct heat away from the die to the package top. The thermal resistance of the package to the top is the JC (junction-to-case) and is specified at 0.53C/Watt. In order to calculate what type of heatsinking should be applied to the EDGE7725, the designer needs to determine the worst case power dissipation of the device in the application. The graph above gives a good visual relationship of the range of power dissipation that can be expected from the E7725. The range of power covers the different modes of operation, power supply settings, and performance bias
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
Required Heatsinking Thermal Resistances
Covers Complete Range of Supplies and Modes R of Heatsink System ( C/W) 12.0 10.0 8.0 6.0 4.0 2.0 0.0 Lowest Supplies Mode0 Lowest Supplies Mode1,2,3 (Max Loads) DUTIO-2/+7 Supplies Mode0 DUTIO-2/+7 Supplies Mode1,2,3 (Max Loads) Highest Supplies Mode0 Highest Supplies Mode1,2,3 (Max Loads)
More information on heatsink system selections can be read on heatsink vendors' web sites and in the Semtech Application Note #ATE-A2 Cooling High Power, High Density Pin Electronics.
Protection Considerations The EDGE7725 has ESD protection on its inputs and outputs as well as programmable clamps on its comparator's inputs. The appropriate circuit (e.g. parallel R and C) may need to be added to the comparator inputs and load outputs to protect against more stressful conditions; for example, a short to a high voltage power supply.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
EDGE7725 as a Dual Driver with Dual Comparators With the load powered down (see Table 1), the load consumes minimum power, and the EDGE7725 acts as a Dual Driver with Dual Comparators as shown below. If the loads are never to be used in a certain circuit, their VCM_IN inputs should be connected to GND, and other inputs and outputs can be open-circuit. No capacitors are required on VCM_CAP or VCM_OUT. With Driver tri-level enabled (Table 1), then the LEN/LEN* inputs to each channel provide tri-level switching.
Channel 0
DBIAS[0] DVH[0] LEN[0] LEN*[0] DEN[0] DEN*[0] RADJ[0] DOUT[0] FADJ[0] DVL[0] DVT[0] SEL_CMP VCC
QA*[0] QA[0] CBIAS[0], PECL[0] QB[0] QB*[0] DHI[0] DHI*[0]
CVA[0] VCH[0] VINP[0] VCL[0] CVB[0]
VEE
CVC[0] SEL_DHI SEL SEL CVC_GND[0:1] CVC[1] VEE
DHI*[1] DHI[1] QB*[1] QB[1] CBIAS[1], PECL[1] QA[1] QA*[1]
CVB[1] VCL[1] VINP[1] VCH[1] CVA[1]
VCC DVT[1] DVL[1] FADJ[1] DEN*[1] DEN[1] LEN*[1] LEN[1] DVH[1] DBIAS[1] DOUT[1] RADJ[1]
Channel 1
ANODE CATHODE
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
E7725 Hookup
VEEs of both channels must be connected together; same for VCC, PECL and GND. NOTE: All capacitors are 0.1F unless otherwise noted.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Package Information
14 x 20 x 2.0 mm, 128-Pin MQFP Package (with Exposed Metal Heat Slug on Top)
10 TYP.
RAD. 2.92 .50 (2X)
A2 A1 10 TYP.
A
e
-A- 2.54 .50
-B-
D1
D
DIMS.
EXPOSED HEAT SINK HEATSINK INTRUSION 0.0127 MAX. -D- E1 E
TOL. MAX MIN / MAX .10 .20 .10 .20 .10 .15 BASIC 2.35 0.00 / 0.25 2.00 23.20 20.00 17.20 14.00 .88 .50 0.19 min / 0.27 max 0 - 7 4 MAX MAX 6 .08 .08
A A1 A2 D D1 E E1
Top View
L e b 1 ddd ccc
.30 RAD. TYP.
0.20 RAD. TYP.
01
STANDOFF
A
A1
.25 SEATING PLAN
.17 MAX
0
L
b
ddd M C A-B S D S
-C-
LEAD COPLANARITY
ccc C
NOTES: 1) All dimensions in mm. 2) Dimensions shown are nominal with tol. as indicated. 3) L/F: EFTEC 64T copper or equivalent, 0.127 mm (.005") or 0.15 mm (.006") THICK. 4) Foot length "L" is measured at gage plane at 0.25 above the seating plane. 5) Lead finish 85/15 Sn/Pb.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Absolute Maximum Ratings
Parameter VCC (relative to GND) VEE (relative to GND) Total Power Supply Comparator Supply Digital Input Voltages Digital Differential Input Voltages Digital TTL Inputs Input Voltages Voltage Inputs Load Voltages Current Inputs Analog Input Currents Symbol VCC VEE VCC - VEE PECL DHI(*), DEN(*), LEN(*) DHI(*), DEN(*), LEN(*) CONFA, CONFB VINP, CVA, CVB, CVC, DVH DVL, DVT, VCM_IN, VCH, VCL (VCC-VCM_IN), (VCM_IN-VEE), (VCC-LOUT), (LOUT-VEE) ISC_IN, ISK_IN, RADJ, FADJ, CBIAS, DBIAS ISC_IN, ISK_IN RADJ, FADJ DBIAS, CBIAS QA/QA*; QB/QB* Iout DVH - DVL LOAD - VCM_IN TS TJ TSOL -1.0 VEE -2.5 -2.5 VEE 0 -0.5 0 0 0 0 -40 0 -11 -65 Min 0 -6.5 Max +11.75 0 +18.25 +5.5 VCC +2.5 VCC VCC 14.5 2.5 2 2 2 50 +40 11.5 +11 +150 +125 +260 Units V V V V V V V V V V mA mA mA mA mA V V C C C
Digital Output Currents Per Pin Driver Output Current Driver Swing Load Input Voltage Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 0.25" from the pin)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those "recommended", is not implied. Exposure to conditions above those "recommended" for extended periods may affect device reliability.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Recommended Operating Conditions
Parameter Positive Power Supply Negative Power Supply (Note 1) Total Analog Supply Comparator Output Supply CVC_GND Compliance Analog Inputs Driver Bias Current Comparator Bias Current Driver Slew Rate Adjustments Voltage Clamps Load Commutating Voltage Source, Sink Currents Thermal Resistance of Package (Note 2) Junction Temperature
Symbol VCC VEE VCC - VEE PECL CVC_GND DBIAS CBIAS RADJ, FADJ VCH VCL VCM_IN ISC_IN, ISK_IN JC TJ
Min +8.0 -6.25 12.2 +3.0 -0.3 0.7 0.5 0.3 VEE + 5.5 VEE + 3.7 VEE + 3.5 0
Typ +10 -5 15.0 +3.3 0
Max +11.6 -4.2 17.85 +4.5 +0.3 1.15 1.25 1.4 VCC - 3.8 VCC - 5.5 VCC - 3.5 1.78
Units V V V V V mA mA mA V V V mA C/W
0.53 +40 +100
C
Note 1: Note 2:
For `Negative' ECL "Flex" inputs (DHI, DEN, LEN) with range down to -2V input voltage, VEE < -4.75V. Measured at top of package on exposed heat slug.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS DC Characteristics
Parameter Configuration Inputs (CONFA, CONFB, SEL_DHI, SEL_CMP) Input Low Level Input High Level Input Bias Current SEL_DHI CONFA, CONFB, SEL_CMP Parameter DCL Node Leakage Characteristics All Off (Mode 0, DEN = 0) Drive/Receive (Mode 1, LEN = DEN = 0, Clamps Off) Drive/Receive with DVT (Mode 2, DEN = 0) Drive Pin (Mode 3, DEN = 0) IDCL_LEAK IDCL_LEAK IDCL_LEAK IDCL_LEAK -10 -20 -20 -10 +10 +20 +20 +10 A A A A VIL VIH IIN IIN Symbol 0 2 -25 -3 Min Typ 0.8 5 +25 +3 Max V V A A Units Symbol Min Typ Max Units
DC test conditions (unless otherwise specified): Over the full "Recommended Operating Conditions".
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EDGE7725
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
Parameter DRIVER Circuit (no Load unless otherwise specified) Output Range Analog Inputs High Level Low Level Symbol Min Typ Max Units
DOUT DOUT DVH DVH DVL, DVT DVL, DVT DOUTSW
-2.0 VEE + 3.7 VEE + 4.0 -1.5 VEE + 3.5 -2.25 0.1 -50 0.7 0.3 -0.2
+7.0 VCC - 3.8 VCC - 3.5 +7.4 VCC - 4.0 +6.5 8.0 +50 1.15 1.4 +2.0 100 250 +35 7.5 +150 0.5 1.0 +10 +5.0 2.0 +100 3.0
V V V V V V V A mA mA V mV mV mA mV mV/C V/V mV V V A pF
Driver Swing Input Current Driver Bias (Note 4) Slew Rate Adjustments (Note 4) RADJ, FADJ, DBIAS Voltage Compliance Part-to-Part Variation @ Imin Part-to-Part Variation @ Imax Driver Output (Note 1) DC Output Current Output Impedance (@ 25 mA) (Note 3) DC Accuracy (Note 1) Offset Voltage (@ DVT = DVH = DVL = 0) Offset Tempco (@ DVL = DVT = 0V, DVH = 3V) Gain (Measured @ allowable -FS and +FS) Linearity Digital Inputs (DHI, DEN) Input Voltage Range (Note 2) Differential Input Swing Input Current Input Capacitance I_in DBIAS RADJ, FADJ VDBIAS, VRADJ, VFADJ VDBIAS, VRADJ, VFADJ VDBIAS, VRADJ, VFADJ Imax Rout DVT, DVH, DVL - DOUT DOUT/C DOUT/DVT, DVH, DVL DOUT INL DHI(*), DEN(*) |Input - Input*| Iin Cin
-35 4.0 -100 0.975 -10 -2.0 0.24 -100
5.5
DC conditions (unless otherwise specified): Over the full "Recommended Operating Conditions". Note 1: Note 2: Note 3: Note 4: See Applications Section describing the applicable "DRIVER OUTPUT RANGE" as a function of VCC and VEE. Digital Input Voltage Range also > (VEE + 2.75V). Typical value of Rout should be used to calculate the external resistor for matching to the application's transmission line impedance. All DC characteristics tested with DBIAS = 0.7mA, RADJ = FADJ = 0.7mA.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
Parameter COMPARATOR Circuits (CBIAS = 0.5mA) Analog Inputs Voltage Range Symbol Min Typ Max Units
CVA, CVB CVA, CVB CVC ICVC ICVA, ICVB, ICVC CBIAS CBIAS CBIAS CBIAS VINP VINP VINP |VINP[0]-VINP[1]| VHYS Vos Vos |QA - QA*|, |QB - QB*| (QA + QA*) / 2, (QB + QB*) / 2
VEE + 3.6 -2.15 -800 -50 -100 0.5 -0.2
VCC - 3.65 +7.25 +800 +50 +100 1.25 +2.0 200 350
V V mV A A mA V mV mV V V V V mV
Input Current Input Current (VEE +2.0V < V < VCC - 1.25V) Comparator Bias CBIAS Voltage Compliance Part-to-Part Variation @ 0.5 mA Part-to-Part Variation @ 1.25 mA VINP Range of Window Comparator VINP Range of Differential Comparator Differential Range of Differential Comparator (Note 1) VINP Hysteresis Offset Voltage Window Comparators Differential Comparators Differential Output Swing (Note 2) Common Mode Output Range
VEE + 3.7 -2.0 VEE + 3.7 0.1 15 -10 -30 400 PECL - 1.6
VCC - 3.8 7.0 VCC - 4.7 1.0
+10 +30 550 PECL - 1.2
mV mV mV V
DC test conditions (unless otherwise specified): Over the full "Recommended Operating Conditions". Note 1: Note 2: To achieve a differential of 1V, then VEE < -4.7V Window comparators need 30 mV of overdrive to meet the minimum differential output swing.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
Parameter COMPARATOR Voltage Clamps Voltage Clamp Range (Clamps On, VC_OFF=0) Symbol VCH VCH VCL VCL VCH - VCL IVCH IVCL VCH - VCL ICLAMP ICLAMP ICLAMPSC Tsc 100 Min VEE + 5.5 -0.25 VEE + 3.7 -2.05 +1.0 -20 -20 Typ Max VCC - 3.8 +7.1 VCC - 5.5 +4.4 Units V V V V V A A V A mA mA ns
Voltage Clamp Difference (Note 2) Voltage Clamp Input Currents VCH (VEE + 4V < VCH < VCC - 1.25V) VCL (VEE + 1.25V < VCL < VCC - 4V) Clamp Disable Voltage (Note 2) Clamp Current, Dynamic (Note 1) @ VCLAMP = 0V @ VCLAMP = 0.6V Clamp Current, Static, Short Circuit (measured 2 volts above/below VCH/VCL) Short Circuit Protection Delay Timing (Note 3) Clamp Accuracy Offset Voltage (ICLAMP = 100 A, VCLAMP = -FS)
+20 +20 0.0 600
15
30 40 200 100
VOS
-160
+160
mV
DC test conditions (unless otherwise specified): Over the full "Recommended Operating Conditions". Note 1: Clamp Characteristics:
VCL VCH
-ICLAMP -VCLAMP
+ICLAMP +VCLAMP
Note 2: Note 3:
If (VCH - VCL) < 1.0V, then the clamp function is indeterminate between being active and turning off. A difference of zero volts or negative will ensure the clamps are turned off. Short circuit protection delay time is the period of time that the clamp circuit will provide high dynamic clamp current before switching into the lower, short circuit current condition.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
Parameter LOAD Circuit Source/Sink Currents @ ISK_IN = ISC_IN = 0 to 20 A (Note 3) @ ISK_IN = ISC_IN = 1.78 mA (Note 1) Current Programming Inputs Input Voltage @ ISK_IN, ISC_IN =0 to 1.78 mA Commutating Voltage Range Commutating Voltage Output, SNK Voltage Input Input Voltage into Load Load Differential Voltage Commutating Buffer Input Current @ VCM_IN Load Enabled (LE high, Load On) Input Voltage Range (Note 2) Differential Input Swing Input Current Load Output Impedance (ILOUT = 32mA) VCM Buffer Accuracy Offset Voltage (@ VCM_IN = 0V) Current Source Accuracy Source/Sink Current Turn-On Point (Note 1) Source /Sink Current Gain (Note 1) Source/Sink Linearity (Note 4) VCM_OUT - VCM_IN ISC, ISK Ai -185 20 20 -200 +185 40 24 +200 mV A A IVCM_IN LEN, LEN* |LEN - LEN*| ILEN, ILEN* ZLOUT 0 -2.0 0.24 -100 5 7 +10 +5.0 2.0 +100 9 A V V A Imin Imax V(ISK_IN), V(ISC_IN) VCM_IN VCM_IN VCM_OUT, SNK VCM_OUT, SNK LOUT LOUT |LOUT - VCM_IN| 20 32 -0.4 VEE + 3.5 -2.2 VEE + 3.7 -2 VEE + 3.7 -2 0.75 +0.3 VCC - 3.5 +7.3 VCC - 3.8 +7 VCC - 3.8 +7 +10 A mA V V V V V V V V Symbol Min Typ Max Units
DC test conditions (unless otherwise specified): Over the full "Recommended Operating Conditions". Note 1: Note 2: Note 3: (VCM_IN + 0.75V) < LOUT, or LOUT< (VCM_IN - 0.75V). Load Enable Input Voltage also > (VEE + 2.75V). Load characteristics:
LOUT Source Out <10 A <10 A >20 A ISC_IN ISK_IN Sink Out
Note 4:
Calibrated at input points of 100A, 500A, 1mA, 1.4mA.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
Parameter Power Supply Currents PECL Power Supply Current Mode 0 - All Off - Lowest Power (Driver, Comp, Load Powered OFF) Positive Supply Negative Supply Modes 1, 2, 3 - Higher Power Positive Supply Negative Supply IPECL 155 176 198 mA Symbol Min Typ Max Units
ICC IEE ICC IEE
-421
350 -365 406 -430
409
mA mA mA mA
480
-500
DC conditions: DVL = 0V, DVH = 3V, CVA = 0.5V, CVB = 2.4V, CVC = 1V, VCM_IN = 0V, ISK = ISC = 0 mA, PECL = 3.3V, comparator outputs terminated 50 to PECL -2V. All conditions with DHI[0:1], SEL_DHI, SEL_CMP = Low. Designers should add the maximum currents expected for the programmable Load functions to the respective power supplies (ICC and/or IEE). CBIAS = 0.5mA, DBIAS = 0.7mA, RADJ = FADJ = 0.7mA.
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics
Test Circuit AC Test Circuit
50 Transmission Line (20 inches, ~2 ns) (2 ns not included in any propagation delay specs) Measurement Point "OUT"
3.3nH VINP
(RL) 953
Oscilloscope 50
C
3.9nH LOAD
C
VSWING 0.8V (ECL) 0.3V (LVDS) 0.3V (LVTTL) 5.0V (CMOS/TTL)
45.3 DOUT
3pF 3pF 5pF 8pF
3pF
Parameter Configuration Inputs Settling Time of CONFA, CONFB, SEL_DHI, SEL_CMP
Symbol
Min
Typ
Max 100
Units ns
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
Parameter LOAD Circuit Propagation Delay (Note 1) Inhibit to Iout (to 90% of programmed Iout) Iout to Inhibit (to 10% of programmed Iout) Output Capacitance Load Active (ISC_IN, ISK_IN = 0) Load Off COMPARATOR Circuits Propagation Delay (Figure 4 with VINP 0.4V to 1.2V) (Note 6) Input Waveform Tracking (Figure 6) (Note 6) (3V step, 100 ps error, 0.6V to 2.4V) Dispersion Related Specifications Common Mode Dispersion (Note 6) (Figure 2) Pulse Width (Notes 2,6) (Figure 3) Overdrive (from 200 mV to 800 mV, 1V/ns slew rate) (Figure 4) (Note 6) Delay Symmetry (same comparator) (0 to 800 mV input) (Figure 4) Slew Rate (Figure 5) (Note 6) COMP_A to COMP_B Delay Matching (Figure 4) Differential Delay Tracking (VINP1 vs VINP0 in differential mode) (Figure 4) Input Capacitance Digital Output Rise and Fall Times (20% - 80%) (into 50 load to (PECL - 2V)) Delay TempCo (Note 6) DRIVER Circuit Propagation Delay (0 to 800 mV Output) (Note 1) Data (DHI) to Output (Figure 10) Output Active to HiZ (Figure 9) HiZ to Output Active (Figure 9) Rise/Fall Times (Figure 11) 0 to 800 mV (20% - 80%) 0 to 3V (10% - 90%) 0 to 3V (10% - 90%) (Note 3) 0 to 5V (10% - 90%) Crossover Voltage Error (Figure 15) TPLH, TPHL TPAZ TPZA Tr/Tf Tr/Tf Tr/Tf Tr/Tf VXOVER 1.0 1.25 2.0 2.0 2.5 4.0 0.3 0.9 1.2 55 ns ns ns ns ns ns ns % TPLH, TPHL |TPHL - TPLH| Tpd |TPLH - TPLH| or |TPHL - TPHL| |TPLH - TPLH| or |TPHL - TPHL| Cin Tr, Tf Tpd/C 4.9 200 2.5 250 25 25 35 TPLH, TPHL 1.0 70 50 50 60 50 10 30 ps ns ps ps ps ps ps pF ps ps/C TPLH, TPHL 0.5 3.0 1.5 ns V/ns Tpd_on Tpd_off Cout Cout 2.25 2.25 2.7 2.3 3.2 3.2 3.5 3.5 ns ns pF pF Symbol Min Typ Max Units
0.7 1.5 1.0 45
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
Parameter DRIVER Circuit (continued) Fmax (Note 4) (Figure 12) 0 to 800 mV 0 to 3V 0 to 5V Fmax (RL=50, swing = programmed value) (Note 4) (Figure 14) 0 to 0.5V 0 to 1.0V 0 to 3.0V Minimum Pulse Width (Note 4) (Figure 8) 0 to 800 mV 0 to 3V 0 to 5V Pulse Width Dispersion to Minimum Pulse Width (PWmin = 0.8 ns) (Figure 7) Driver-to-Driver Skew (Diff. Driver Mode) (Note 5) Output Capacitance Delay Tempco (Figure 10) (Switching DVH and DVL) Delay Symmetry (same driver, 0.8V swing) (Figure 10) DVT Enable/Disable Times (Figure 13) DVL to DVT DVT to DVL DVH to DVT DVT to DVH Trans. Time Matching (same driver) (Figure 11) DOUT = 0.8V DOUT = 3.0V DOUT = 5V Overshoot/Undershoot (Figure 14) DOUT = 0.8V DOUT = 3.0V DOUT = 5V Ringback (Figure 14) DOUT = 0.8V DOUT = 3.0V DOUT = 5V Voltage Crosstalk (when switching adjacent channel) DOUT = 0.8V DOUT = 3.0V DOUT = 5V Timing Crosstalk DOUT = 0.8V DOUT = 3.0V DOUT = 5V Cout Tpd/C |TPHL - TPLH| TPLT TPTL TPHT TPTH Tr,f Tr,f Tr,f 0 0 0 3.0 2.0 3.25 2.0 7.0 1.5 2.0 100 4.5 3.5 4.5 3.5 100 100 150 100 150 300 50 100 200 10 10 10 10 10 10 Fmax Fmax Fmax 500 300 200 MHz MHz MHz Symbol Min Typ Max Units
Fmax Fmax Fmax Tpw+, Tpw-
900 450 400 0.6 1.2 1.5
MHz MHz MHz ns ns ns ps ps pF ps/C ps ns ns ns ns ps ps ps mV mV mV mV mV mV mV mV mV ps ps ps
Tpw
125 60
AC test conditions (unless otherwise specified): "Recommended Operating Conditions". VCC = +10V, VEE = -5V, DBIAS = 0.7mA, RADJ = 0.7mA, FADJ = 0.7mA, CBIAS = 0.5mA. Note 1: Propagation delays for LV_PECL, differential logic inputs. LOUT has 50 to GND for Load tests. Note 2: For 800 mV input while maintaining Tpd Error <100 ps. Note 3: Min Rise/Fall Times for RADJ = FADJ = 0.3 mA. Note 4: At 10% output amplitude attenuation. Note 5: 0 to 800 mV outputs. Note 6: Applies to single-ended and differential comparators.
(c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
INPUT: Freq = 10 MHz; 1.0V pp; -1V < Vos < 6.0V 50% duty cycle, 20-80% Tr,f = 1.0 ns VINP
+6.0V
CVA/B = 50%
CVA/B = 50% 0.0V -1.0V CVA/B = 50%
Time
(QA - QA*)
0.0V
TPLH
TPHL
Time
The measured result is the maximum absolute value change in TPLH or TPHL over the different common mode levels. Figure2. Comparator Dispersion: Common Mode Measurement Definition
INPUT: Period = 50 ns; 0.8V pp Tpw,in1 = 50 ns - PWmin Tpw,in2 = PWmin 20-80% Tr,f = 0.25 ns for Highest Performance spec; 0.5 ns for Lower Performance Spec VINP
0.8V
CVA/B = 0.4V
0.0V Tpw,in1 Tpw,in2 Tpw,out1 Tpw,out2
Time
(QA - QA*)
0.0V
Time
The measured result is the maximum absolute value change in [Tpw,in - Tpw,out] as the P.W. changes from 25 ns to the endpoints of PWmin and [50ns - PWmin]. Figure 3. Comparator Dispersion: Pulse Width Measurement Definition (c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
INPUT: Freq = 10 MHz; 0.4V < VPP < 1.6V; Vos = 0.8V; 50% Duty Cycle, SR = 1V/ns
VINP
1.6V 1.0V 0.8V 0.6V 0.0V
CVA/B = 0.8V
Time
TPLH TPHL
(QA - QA*)
0.0V
Time
The measured result is the maximum absolute value of the change in TPLH or TPHL when the overdrive changes from 800 mV to 200 mV. Figure 4. Comparator Dispersion: Overdrive Measurement Definition
VINP
1.0V
INPUT: Freq = 10 MHz; 0-1.0V; 50% Duty Cycle; 0.5 ns 20-80% Tr,f 2.0 ns
CVA/B = 0.50V
0.0V
Time
Tpd(+) Tpd(-)
(QA - QA*)
0.0V
Time
The measured result is the maximum absolute value of the change in Tpd(+) or Tpd(-) as the input signal slew rate changes from minimum to maximum as defined in the figure. Figure 5. Comparator Input Slew Rate Measurement Definition
(c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
INPUT: Freq = 10 MHz; 0-VHI; 50% Duty Cycle; VINP
VHI 2.0V CVA/B = 80% Vhi
CVA/B = 50% Vhi
0.0V
CVA/B = 20% Vhi TPHL1
Time
(QA - QA*)
0.0V
TPLH1
Time
TPHL2
(QA - QA*)
0.0V
TPLH2
Time
TPHL3
(QA - QA*)
0.0V
TPLH3
Time
The measured result is the maximum absolute value of the change in Tpd(+) or Tpd(-) among the three measurement points for each edge as depicted above. Figure 6. Comparator Dispersion: Waveform Tracking Measurement Definition
(c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
Period = 50 ns Tpw, in1 = 50 ns Tpw, in2 = PWmin
Tpw,in1 Tpw,in2
PWmin
(DHI
DHI*)
0.0V
Time
OUT
OUTPUT: OUT(H) = 0.8V; OUT(L) = 0.0V
0.4V
0.0V Tpw,out2 Tpw,out1
Time
Tpw = |(Tpw, in1
Tpw, out1)
(Tpw, in2
Tpw, out2)|
The measured result is the maximum absolute value of the change in [Tpw,in - Tpw,out] as the P.W. changes from 25 ns to the endpoints of PWmin and [50ns - PWmin]. Figure 7. Driver Dispersion: Pulse Width Measurement Definition
OUT Tpw+ VOH VOL + 0.9 * (VOH-VOL) Tpw-
Output Signal
(VOH+VOL)/2
VOL + 0.1 * (VOH-VOL) VOL Time
Figure 8. Driver Minimum Pulse Width Measurement Definition
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
(DEN - DEN*)
0.0V
Time
OUTPUT: DVH = 0.8V, DVL =-0.8V OUT DVH
+800mV 90% TPZA TPAZ
10% 0.0V 10%
Time
DVL
90% -800mV (RLOAD at OUT = 50 to GND)
Figure 9. Driver HiZ Enable/Disable Delay Measurement Definition
OUTPUT: OUT(H) = 0.8V; OUT(L) = 0.0V (DHI - DHI*)
0.0V
Time
OUT
+0.8V
TPLH
TPHL
+0.4V
0.0V
Time
Figure 10. Driver Propagation Delay: DHI to OUT, Symmetry, and Tracking Skew Measurement Definition
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
OUT
OUT(H) V1
Tr
Tf
V2 0.0V
Time
V1 is 0.9 * OUT(H) for 3V and 5V, 0.8 * OUT(H) for 0.8V and lower V2 is 0.1 * OUT(H) for 3V and 5V, 0.2 * OUT(H) for 0.8V and lower
Figure 11. Driver Transition Times and Transition Time Matching Measurement Definition
OUT
1 / Fmax OUT(H)
0.90 OUT(H)
0.0V
Time
Figure 12. Driver Fmax Measurement Definition
(c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
(LEN LEN*)
0.0V
Time
OUT (DVT)
0V 20% TPLT TPTL
Driver in LOW state, DHI < DHI*
(DVL)
80% 800mV
Time
OUT (DVH)
+800mV 80%
TPHT
TPTH
Driver in HIGH state, DHI > DHI* (DVT)
20% 0V
Time
Figure 13. Driver DVT (Third Driver Level) Enable/Disable Delay Measurement Definition
OUT
V2
overshoot
ringback
V1
0.0V
ringback undershoot
Test Cases: V1:V2 = DVL:DVH = DVT:DVH = DVL:DVT
Figure 14. Driver Overshoot, Undershoot, and Ringback
DVH to DVL XOVER DVL to DVH
800 mV
0V
Figure 15. Driver Output Crossover Voltage Measurement (c)2006 Semtech Corp. , Rev. 9, 8/22/06
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EDGE7725
TEST AND MEASUREMENT PRODUCTS Ordering Information
Model Number E 7725A X F EVM7725AXF
P ackag e 14 x 20 x 2.0mm, 128-Pin MQFP with Exposed Heat Slug EDGE7725 Evaluation Board
Contact Information
Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633
(c)2006 Semtech Corp. , Rev. 9, 8/22/06
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